ISSCC 2007 / SESSION 17 / ANALOG TECHNIQUES AND PLLs / 173

17.7 A Double-Tail Latch-Type Voltage Sense Amplifier input and output pads (for probe station measurement) was with 18ps Setup+Hold Time placed on the same die. The layout of the double-tail SA is shown in the inset of the chip micrograph in Fig. 17.7.7. An SR-latch is Daniel Schinkel, Eisse Mensink, Eric Klumperink, Ed van Tuijl, connected to the output of the SA to create static output signals Bram Nauta without loss of timing information from the core of the SA. When required, more advanced 'slave' stages could be used in applicaUniversity of Twente, Enschede, The Netherlands tions [3].